The present invention relates to a semiconductor device and manufacturing technology thereof, in particular, to a technology effective when applied to a semiconductor device having a non-volatile memory such as electric erasable programmable read only memory (which will hereinafter be called “flash memory”, simply).
In Japanese Unexamined Patent Publication No. 2001-185633 (Patent Document 1), disclosed is an EEPROM device fabricated on a single conductive layer formed on a semiconductor substrate, while being insulated via an insulation layer; wherein the EEPROM device is a single level poly EEPROM device whose area per bit can be reduced.
In Japanese Unexamined Patent Publication No. 2001-257324 (Patent Document 2), disclosed is a technology capable of improving a long-term data holding performance in a nonvolatile memory device formed by a single layer poly-flash technology.    [Patent Document 1] Japanese Unexamined Patent Publication No. 2001-185633    [Patent Document 2] Japanese Unexamined Patent Publication No. 2001-257324